The present invention relates to a bridging technique for high-level synthesis which converts data describing an algorithm of hardware using a highly abstract program description language such as C language into a system level description language such as System C which can describe functions specific to hardware such as the time concept or parallel processing, and relates to a compilation method which works as abridge to high-level synthesis, for example, and further to a technique effectively applicable to compilers.
While limitations of the Register Transfer Level (RTL) design is being alarmed as System-on-Chip semiconductor integrated circuits (also simply referred to as SoC) have become more highly integrated and more complicated, an approach of efficiently performing hardware design is becoming widespread, which uses a hardware model (simply referred to as HW model hereinafter) described based on C language or C++ language which are more highly abstract than the hardware description language (HDL). As representative techniques, there are high-level synthesis techniques which generate RTL from a hardware model or hardware/software co-verification techniques using virtual platforms.
Since pure C language or C++ language cannot express the concept of time, parallel processing, or the like, it is difficult to describe functions specific to the hardware. Therefore, a system level description language (e.g., SystemC, etc.) with an ability of expressing the hardware added to C language and C++ language is used for developing HW models.
The high-level synthesis technique is a technique of automatically generating an RTL with the system level description language as the input, and aims at reducing the TAT (turn-around time) for developing various products. As a currently wide-spread high-level synthesis tool, there is the Cynthesizer, which is a product of Forte Design Systems.
The hardware/software co-verification technique using a virtual platform is a technique which allows high-speed co-verification simulation at a stage earlier than completion of the hardware, by designing a system including hardware and software using a common system level description language. As a virtual platform, there is the Platform Architect, which is a product of Synopsys.
In order to employ the techniques described above, it is necessary to create a HW model using system level description language based on the C language description of a part to be the hardware. However, no useful technique is provided to work as a bridge to high-level synthesis, which has been performed manually. For example, a part related to input from and output to the outside of the model, i.e., extracting a variable of outside access with a bus or memory, wrapping the target algorithm for the extracted I/O port, and defining exchange between the variable corresponding to external access and the port, are manually performed.
On the other hand, as a technique which does not take into consideration bridging to such high-level synthesis, there is one described in Patent Document 1 (Japanese Patent Laid-Open No. 2003-216668), for example. According to Patent Document 1, an integrated circuit is designed by defining its function using a programming language which supports parallel processing and synchronous communication, an acquired source code is given to a compiler, and the compiler generates, via an optimizer module which changes the timing of synchronous communication without changing the order of external communication of the integrated circuit, an output code by HDL expressing the circuit configuration of the integrated circuit.